注: 啃手册自用,基于riscv-spec-20191213-1版本,使用DeepL辅助翻译,人工二次修改校对,若有纰漏,望谅指正.

riscv-spec

Chapter 9 “Zicsr” CSR

“Zicsr”, 控制和状态寄存器(CSR) 指令, Version 2.0

RISC-V 定义了一个由 4096 个控制和状态寄存器及其Hart(硬件线程)组成的独立地址空间。本章定义了在这些 CSR (控制和状态寄存器)上运行的全套 CSR 指令.

RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart. This chapter defines the full set of CSR instructions that operate on these CSRs.

虽然 CSR 主要在特权模式下使用，但在非特权模式中也有一些用途,包括计数器和定时器以及浮点状态. 计数器和定时器不再被视为标准基本,因此，访问它们所需的 CSR 指令已从基本 ISA 章移至本章.

While CSRs are primarily used by the privileged architecture, there are several uses in unprivi-leged code including for counters and timers, and for floating-point status. The counters and timers are no longer considered mandatory parts of the standard base ISAs, and so the CSR instructions required to access them have been moved out of the base ISA chapter into this separate chapter.

9.1 CSR 指令

所有的CSR指令都是对于单个CSR读/修改/写的原子操作,其12位编号被编码到指令的[31:20]位.立即数零扩展(注:高位补零)到5位后,被编码到rs1字段.

All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.

CSRRW(Atomic Read/Write CSR)指令,原子化地交换整数寄存器和CSR的值. CSRRW读取CSR原有的值,零扩展到XLEN位后,写入rd整数寄存器. rs1寄存器的初始值被写入CSR. 如果rd=x0,那么指令不会读取CSR,以免做副作用(side effects).

The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer registers. CSRRW reads the old value of the CSR, zero-extends the value to XLEN bits, then writes it to integer register rd. The initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

CSRRS（Atomic Read and Set Bits in CSR）指令读取 CSR 的值，将其零扩展到 XLEN 位，并写入整数寄存器 rd。整数寄存器 rs1 中的初始值被视为位掩码，用于指定 CSR 中要设置的位位置。如果 CSR 位可写，rs1 中的任何高位都将导致 CSR 中的相应位被设置。CSR 中的其他位不会受到影响(虽然写入CSR的时候可能会做一些副作用)

The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written).

CSRRC（Atomic Read and Clear Bits in CSR）指令,读取 CSR 的值，将其零扩展到 XLEN 位，并写入整数寄存器 rd。整数寄存器 rs1 中的初始值被视为位掩码，用于指定 CSR 中要清除的位位置。如果 CSR 位可写，rs1 中的任何高位都将导致 CSR 中的相应位被清零。CSR 中的其他位则不受影响。

The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected.

对于 CSRRS 和 CSRRC，如果 rs1=x0，则指令根本不会写入 CSR, 诸如此类对于CSR写入的副作用都会被避免，例如在访问只读 CSR 时会直接引发非法指令异常。但 CSRRS 和 CSRRC 指令始终会读取 CSR ，无论 rs1 和 rd 是多少(所以可能会做副作用)。需要注意的是，如果 rs1 指定的寄存器虽然不是x0, 但是如果其值是0，指令仍会尝试将未修改的值(注:因为掩码为0)写回 CSR，做副作用。对于一个 CSRRW 指令, 如果 rs1=x0, 则将尝试向目标 CSR 写入零值。

For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.

CSRRW、CSRRS 和 CSRRC 指令的变体: CSRRWI、CSRRSI 和 CSRRCI, 他们功能类似，但它们更新 CSR 时使用的是将 rs1 字段编码的 5 位无符号立即值（uimm[4:0]）字段零扩展到 XLEN 位得到的值，而不是整数寄存器中的值。对于 CSRRSI 和 CSRRCI，如果 uimm[4:0] 字段为零，则这些指令不会写入 CSR，也不会导致 CSR 写入时可能出现的副作用。对于 CSRRWI，如果 rd=x0，则指令不会读取 CSR，也不会导致 CSR 读取时可能产生的副作用。无论 rd 和 rs1 字段如何，CSRRSI 和 CSRRCI 都将始终读取 CSR 并可能导致做副作用。

The CSRRWI, CSRRSI, and CSRRCI variants are similar to CSRRW, CSRRS, and CSRRC re-spectively, except they update the CSR using an XLEN-bit value obtained by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the rs1 field instead of a value from an integer register. For CSRRSI and CSRRCI, if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write. For CSRRWI, if rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read. Both CSRRSI and CSRRCI will always read the CSR and cause any read side effects regardless of rd and rs1 fields.

目前定义的 CSR 除了在不允许的访问中产生非法指令异常外，对读取操作没有任何架构上的副作用。定制扩展可能会添加在读取上有做副作用的 CSR 寄存器。

The CSRs defined so far do not have any architectural side effects on reads beyond raising illegal instruction exceptions on disallowed accesses. Custom extensions might add CSRs with side effects on reads.

某些 CSR, 例如 指令退役计数器(instructions-retired counter), instret计数器 可能会因指令执行的副作用而被修改。在这种情况下，如果 CSR 访问指令读取 CSR，则会在指令执行前读取该值。如果 CSR 存取指令写入这样的 CSR，则是写入而不是递增(?)。特别是，一条指令写入 instret 的值将成为下一条指令读取的值。

Some CSRs, such as the instructions-retired counter, instret, may be modified as side effects of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the value prior to the execution of the instruction. If a CSR access instruction writes such a CSR, the write is done instead of the increment. In particular, a value written to instret by one instruction will be the value read by the following instruction.

读 CSR 的汇编伪指令 CSRR rd, csr 编码为 CSRRS rd, csr, x0. 写入 CSR 的汇编伪指令 CSRW csr, rs1 编码为 CSRRW x0, csr, rs1，而 CSRWI csr, uimm 编码为 CSRRWI x0, csr, uimm.

The assembler pseudoinstruction to read a CSR, CSRR rd, csr, is encoded as CSRRS rd, csr, x0. The assembler pseudoinstruction to write a CSR, CSRW csr, rs1, is encoded as CSRRW x0, csr, rs1, while CSRWI csr, uimm, is encoded as CSRRWI x0, csr, uimm.

还定义了其他更多的汇编伪指令，以便在不需要旧值时设置和清除 CSR 中的位： CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.

Further assembler pseudoinstructions are defined to set and clear bits in the CSR when the old value is not required: CSRS/CSRC csr, rs1; CSRSI/CSRCI csr, uimm.